Benchmarking the DEAC Cluster

Understanding Our Hardware

Phase One: Preliminary Work

A Modeling Approach to Hardware Analysis of the Heterogeneous DEAC Cluster

The 2016 International Conference on Computational Science and Computational Intelligence (CSCI)
Symposium on Parallel and Distributed Computing and Computational Science (ISPD)
December 2016

Abstract: The employment of five distinct benchmarks on the Distributed Environment for Academic Computing (DEAC) Cluster at Wake Forest University provides meaningful metrics of cluster processor and memory performance. Given the heterogeneous nature of the DEAC Cluster, the benchmarks taken consider the specific processor architectures comprising the cluster. The data obtained will be assessed via two modeling approaches: (1) linear and polynomial regression and (2) Bayes’ Theorem. The most suitable modeling approach for characterizing the DEAC Cluster is sought through the assessment of these models.

Poster Paper (in press) and Presentation (CSCI-ISPD 2016 Poster)

Phase Two: Current Work

Each benchmark will assess the performance of a different aspect of the DEAC Cluster hardware. Parameters for each benchmark are studied prior to planning and submitting jobs for each benchmark. Data will be obtained when running each benchmark on a single node and on multiple nodes. Results are organized upon job completion.

Current Status of Work:
Jobs running for HPL and IMB are being monitored at present.
Cachebench jobs have completed.
Job submission for IOzone is partially complete.
Benchmarking software for the GPU nodes is in the process of being installed.

Phase Three: Next Steps

Application of regression techniques and Bayes' Theorem to model the results obtained.